Promotional Materials
Deliverables

D1.1 Report on targeted applications, their applications and requirements (IBM, M08)

​D1.2 First report on new algorithmic solutions (TUD, M18)

D1.3 Final report on new algorithmic solutions (TUD, M30)
​
​D2.1 First version programming interface at the micro- and macro-levels (TUE, M12)
​
​D2.2 First backend compiler for micro-instructions (TUE, M18)

D2.3 First version parallelizing orchestrating compiler targeting CIM macro-instructions (INRIA, M24)

D2.4 Complete Parallelization, Orchestration and Compilation Flow (INRIA, M28)

D3.1 Initial macro CIM architecture and CIM-ISA (TUE, M12)

D3.2 Initial communication protocols and infrastructure (ETHZ, M15)

D3.3 Refined CIM architecture (TUE, M27)
​
D3.4 Report on Mapping of Micro-Kernels to Macro-Architecture (ETHZ, M30)

D4.2 Initial models of memristive device (RWTH, M12)

D4.3 Refined Models of Memristive Device (RWTH, M24)

D4.4 Initial memristor crossbar logic / arithmetic and memory design and models (IMEC, M18)

D4.5 Refined memristor crossbar-based logic and memory design and models (IMEC, M34)

D4.6 Initial CIM microarchitecture (IMEC, M18)

D4.7 Refined CIM microarchitecture (IMEC, M34)
The MNEMOSENE project has received funding from the European Union’s Horizon 2020
Research and Innovation Programme under grant agreement No 780215.