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MNEMOSENE
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[20.04.2020] Refined Computation-in-Memory Architecture
 
The MNEMOSENE consortium have recently published the final specification for the instruction set architecture (ISA) for the whole computation-in-memory (CIM) architecture as well as the results of preliminary performance tests.
 
Over the past two years, TU Eindhoven has been leading the consortium’s development of a macro Non-Von Neumann architecture and its CIM-ISA to support storage and computation in the same physical location.
 
So far, tests to evaluate the CIM units using a low-power transport triggered architecture (TTA) have demonstrated major improvements in performance (up to 3.9X faster), energy consumption (up to 69% lower), and combined energy, delay, area product (EDAP) (up to 84% lower).
 
The next step will be to assess the performance of the CIM units with multi-processor system-on-chips, such as the Parallel Ultra Low Power Platform (PULP).
 
To read the related project report, please click on the following link.
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The MNEMOSENE project has received funding from the European Union’s Horizon 2020
Research and Innovation Programme under grant agreement No 780215.
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