[4.1.2021] Reports published on refined memristor crossbar-based logic and memory design and models as well as refined CIM microarchitecture
The MNEMOSENE consortium has recently published two new reports.
The first report covers the refined memristor crossbar-based logic and memory design and models. Led by IMEC, the report investigates, on the lowest hardware level, the impact of memristor array architecture and analogue/digital converter (ADC) design choices on the performance of multiply-and-accumulate (MAC) operations for Resistive Random-Access Memories (ReRAM) based memsristor devices. Also, the report describes work on the optimization of a computation-in-memory (CIM) tile, based on a spin-transfer torque magnetic random access memory (STT-RAM) memristor array, for performing binary logic operations, Matrix-Matrix Multiplication (MMM), or Vector Matrix Multiplication (VMM) operations.
To read the full report on refined memristor crossbar-based logic and memory design and models, please click on the following link.
The second report covers the refined CIM microarchitecture. Led by IMEC, the report presents the work done to further refine the CIM tile architecture, adapt the CIM simulator accordingly, present more detailed performance and energy results, and demonstrate how the design-space exploration can be performed using the CIM simulator.
To read the full report on refined CIM microarchitecture, please click on the following link.
The first report covers the refined memristor crossbar-based logic and memory design and models. Led by IMEC, the report investigates, on the lowest hardware level, the impact of memristor array architecture and analogue/digital converter (ADC) design choices on the performance of multiply-and-accumulate (MAC) operations for Resistive Random-Access Memories (ReRAM) based memsristor devices. Also, the report describes work on the optimization of a computation-in-memory (CIM) tile, based on a spin-transfer torque magnetic random access memory (STT-RAM) memristor array, for performing binary logic operations, Matrix-Matrix Multiplication (MMM), or Vector Matrix Multiplication (VMM) operations.
To read the full report on refined memristor crossbar-based logic and memory design and models, please click on the following link.
The second report covers the refined CIM microarchitecture. Led by IMEC, the report presents the work done to further refine the CIM tile architecture, adapt the CIM simulator accordingly, present more detailed performance and energy results, and demonstrate how the design-space exploration can be performed using the CIM simulator.
To read the full report on refined CIM microarchitecture, please click on the following link.
